Well known RAMs (random access memories) have at least one address port and include storage elements (core cells). In a paper by A. L. Silburt et al entitled "A 180-MHz 0.8-.mu.m BiCMOS Modular Memory Family of DRAM and Multiport SRAM", IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, March 1993, p. 222, at 227 and 228 show various RAM core arrays. In a paper by C. Ohno entitled "Self-Timed RAM: STRAM", FUJITSU Sci. Tech. J., 24, 4, December 1988, p. 293 shows a self-timed RAM which has synchronous operation and an on-chip write pulse generator.
In a paper by F. E. Barber et al, "A 2K.times.9 Dual Port Memory", ISSCC Dig. Tech. Papers, Feb. 1985, pp. 44-45 and in a paper by F. E. Barber et al, "A 200 ns 512.times.10 DUAL PORT RAM", Proc. Electron. Conf., vol. 36, Oct. 1982, pp. 380-382 disclose a single port RAM with two asynchronous address, data and control interfaces. Timing is controlled by arbitration between address latch enable signals. A memory access from port A is initiated by asserting the address latch enable signal "low" on port A, an access from port B is initiated by asserting the address latch enable signal "low" on port B. If port B attempts to access the memory while port A is actively accessing the memory, then an arbitration circuit will delay the port B access until the port A access is complete. In the RAM, asynchronous enables are used to initiate memory access.
In a paper by T. Matsumura et al, "Pipelined, Time-Sharing Access Technique for a Highly Integrated Multi-Port Memory", Symp. VLSI Circuits Dig. Tech. Papers, June 1990, pp. 107-108 and in a paper by K. Endo et al, "Pipelined, Time-Sharing Access Technique for an Integrated Multiport Memory", IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 549-554, April 1991 disclose a dual port memory with respect to a common clock (CLK) which is controlled by common write enable (WE) and chip select (CS) inputs. Likewise, ports 2 and 3 are synchronous with respect to a common clock and control inputs. All inputs for ports 0 / 1 are latched on the rising CLK edge of the port 0 / 1 clock input. All inputs for ports 2 / 3 are latched on the rising CLK edge of the port 2 / 3 clock input. Port pairs 0 / 1 and 2 / 3 are time-multiplexed by their respective clock inputs. Port 0 access is active when the CLK input for ports 0 / 1 is high, port 1 is active when the same clock input is low. Likewise, port 2 is active when the CLK input for ports 2 / 3 is high and port 3 is active when the same clock input is low. Output data is then re-timed in a pipeline cycle and is presented to the outputs relative to the respective rising clock edge. Described is a synchronous time-shared access technique that is dependent on the clock duty cycle (duration of the clock high period and clock low period) with half of the memory accesses occurring while the clock is high and the other half occurring while the clock is low.
The problem is to develop a practical, high-speed, low-power and area efficient read port structure to allow multiple (e.g., eight) random access reads per clock cycle. The straight forward implementation of multiple physical ports throughout the memory would be prohibitively complex and inefficient.